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1/24 march 2003 rev. 2.0 m48t248y m48t248v 5.0 or 3.3v, 1024k timekeeper ? sram with phantom features summary n 5.0v or 3.3v operating voltage n real time clock keeps track of tenths/hundredths of seconds, seconds, minutes, hours, days, date of the month, months, and years n automatic leap year correction valid up to the year 2100 n automatic switch-over and d eselect circuitry n choice of power-fail deselect voltages: (v pfd = power-fail deselect voltage): C m48t248y: 4.25v v pfd 4.50v C m48t248v: 2.80v v pfd 2.97v n full 10% v cc operating range n over 10 years data retention in the absence of power n watch function is transparent to ram operation n 128k x 8 nv sram directly replaces volatile static ram or eeprom figure 1. 32-pin, dip package 32 1 pmdip32 (pm)
m48t248y, m48t248v 2/24 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3. dip connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. dc and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. ac testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 5. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. memory read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. memory write cycle 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 8. memory write cycle 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 7. memory ac characteristics, m48t248y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. memory ac characteristics, m48t248v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. power down/up mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 9. power down/up trip points dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 phantom clock operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 10. comparison register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 clock register information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 clock accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 am-pm/12/24 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 oscillator and reset bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3/24 m48t248y, m48t248v zero bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 10. phantom clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 11. phantom clock read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. phantom clock write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 13. phantom clock reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11. phantom clock ac characteristics (m48t248y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 12. phantom clock ac characteristics (m48t248v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
m48t248y, m48t248v 4/24 summary description the m48t248y/v timekeeper ? ram is a 128kbit x 8 non-volatile static ram and real time clock organized as 131,072 words by 8 bits. the special dip package provides a fully integrated battery back-up memory and real time clock solu- tion. in the event of power instability or absence, a self-contained battery maintains the timekeeping operation and provides power for a cmos static ram. control circuitry monitors v cc and invokes write protection to prevent data corruption in the memory and rtc. the clock keeps track of tenths/hundredths of sec- onds, seconds, minutes, hours, day, date, month, and year information. the last day of the month is automatically adjusted for months with less than 31 days, including leap year correction. the clock operates in one of two formats: C a 12-hour mode with an am/pm indicator; or C a 24-hour mode the m48t248y/v is a 32-pin (pm) dip module that integrates the rtc, the battery, and sram in one package. the modules are shipped in plastic, anti-static tubes (see table 14, page 22). figure 2. logic diagram table 1. signal names figure 3. dip connections a0-a16 v ss dq0-d7 m48t248y m48t248v v cc rst we oe ce ai04661 a0Ca16 address input rst reset input ce chip enable oe output enable input we write enable input dq0Cdq7 data inputs/outputs v cc supply voltage input v ss ground v cc ce m48t248y m48t248v dq3 dq4 dq5 dq6 dq7 a0 a1 a2 a3 oe we a16 nc 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 31 dq1 dq2 v ss dq0 a10 a11 a9 a8 a13 a15 a14 a12 a4 a6 a5 a7 rst ai04662
5/24 m48t248y, m48t248v figure 4. block diagram update dq0 v cc v bat data internal v cc read write 32.768 hz crystal xi xo power fail a0Ca16 dq0Cdq7 clock/calendar logic timekeeper register sram control logic access enable sequence detector comparison register i/o buffers power-fail detect logic rst we oe ce ai04238
m48t248y, m48t248v 6/24 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. soldering temperature not to exceed 260c for 10 seconds (total thermal budget not to exceed 150c for longer than 30 se conds). caution! negative undershoots below -0.3v are not allowed on any pin while in the battery back-up mode. symbol parameter value unit t a operating temperature 0 to 70 c t stg storage temperature (v cc , oscillator off) C40 to 85 c t sld (1) lead solder temperature for 10 seconds 260 c v cc supply voltage (on any pin relative to ground) m48t248y C0.3 to +7.0 v m48t248v C0.3 to +4.6 v v io input or output voltages C0.3 to v cc + 0.3 v i o output current 20 ma p d power dissipation 1 w
7/24 m48t248y, m48t248v dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. dc and ac measurement conditions note: output high z is defined as the point where data is no longer driven (see table 3, page 7). figure 5. ac testing load circuit note: 50pf for m48t248v. table 4. capacitance note: 1. effective capacitance measured with power supply at 5v. sampled only; not 100% tested. 2. at 25c, f = 1mhz. 3. outputs were deselected. parameter m48t248y m48t248v v cc supply voltage 4.5 to 5.5v 3.0 to 3.6v ambient operating temperature 0 to 70c 0 to 70c load capacitance (c l ) 100pf 50pf input rise and fall times 5ns 5ns input pulse voltages 0 to 3v 0 to 3v input and output timing ref. voltages 1.5v 1.5v c l = 50 pf device under test 680 w 1.1 k w v cci ai04240 symbol parameter (1,2) min max unit c in input capacitance 10 pf c io (3) input / output capacitance 10 pf
m48t248y, m48t248v 8/24 table 5. dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. rst (pin 1) has an internal pull-up resistor. 3. all voltages are referenced to ground. sym parameter test condition (1) m48t248y m48t248v unit C70 C85 min typ max min typ max i li (2) input leakage current 0v v in v cc 1 1 a i lo output leakage current 0v v out v cc 1 1 a i cc1 supply current 85 50 ma i cc2 supply current (ttl standby) ce = v ih 510 5 7ma i cc3 v cc power supply current ce = v cci C 0.2 35 23ma v il (3) input low voltage C0.3 0.8 C0.3 0.6 v v ih (3) input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.0 ma 0.4 0.4 v v oh output high voltage i oh = C1.0 ma 2.4 2.4 v v pfd (3) power fail deselect 4.25 4.37 4.50 2.80 2.86 2.97 v v so (3) battery back-up switchover v bat 2.5 v
9/24 m48t248y, m48t248v operation modes table 6. operating modes note: x = v ih or v il ; v so = battery back-up switchover voltage 1. see table 9, page 14 for details. read a read cycle executes whenever write enable (we ) is high and chip enable (ce ) is low (see fig- ure 6). the distinct address defined by the 19 ad- dress inputs (a0-a18) specifies which of the 512k bytes of data is to be accessed. valid data will be accessed by the eight data output drivers within the specified access time (t acc ) after the last ad- dress input signal is stable, the ce and oe access times, and their respective parameters are satis- fied. when ce t acc and oe t acc are not satisfied, then data access times must be measured from the more recent ce and oe signals, with the limit- ing parameter being t co (for ce ) or t oe (for oe ) in- stead of address access. write write mode (see figure 7, page 10 and figure 8, page 11) occurs whenever ce and we signals are low (after address inputs are stable). the most re- cent falling edge of ce and we will determine when the write cycle begins (the earlier, rising edge of ce or we determines cycle termination). all address inputs must be kept stable throughout the write cycle. we must be high (inactive) for a minimum recovery time (t wr ) before a subsequent cycle is initiated. the oe control signal should be kept high (inactive) during the write cycles to avoid bus contention. if ce and oe are low (ac- tive), we will disable the outputs for output data write time (t odw ) from its falling edge. figure 6. memory read cycle note: we is high for a read cycle. mode v cc ce oe we dq7-dq0 power deselect 4.5v to 5.5v or 3.0v to 3.6v v ih x x high-z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high-z active deselect v so to v pfd (min) (1) x x x high-z cmos standby deselect v so (1) x x x high-z battery back-up dq0 - dq7 addresses oe ce data output valid tod todo toe trc tco tacc tcoe tcoe toh ai04230
m48t248y, m48t248v 10/24 figure 7. memory write cycle 1 note: 1. oe = v ih or v il . if oe = v ih during a write cycle, the output buffers remain in a high impedance state. 2. if the ce low transition occurs simultaneously with or later than the we low transition in write cycle 1, the output buffers remain in a high impedance state during this period. 3. if the ce high transition occurs simultaneously with the we high transition, the output buffers remain in a high impedance state during this period. ai04231 dq0Cdq7 addresses we ce data i n stable twr toew tdh tds twc todw twp taw high impedance
11/24 m48t248y, m48t248v figure 8. memory write cycle 2 note: 1. oe = v ih or v il . if oe = v ih during a write cycle, the output buffers remain in a high impedance state. 2. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period. ai04232 dq0Cdq7 addresses we ce data i n stable twr toew twc todw tds tdh tcoe twp taw
m48t248y, m48t248v 12/24 table 7. memory ac characteristics, m48t248y note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. these parameters are sampled with a 5 pf load are not 100% tested. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t dh and t ds are measured from the earlier of ce or we going high. symbol parameter (1) m48t248yC70 unit min max t avav t rc read cycle time 70 ns t avqv t acc access time 70 ns t elqv t co chip enable low to output valid 70 ns t glqv t oe output enable low to output valid 35 ns t elqx t glqx t coe chip enable or output enable low to output transition 5 ns t axqx toh output hold from address change 5 ns t ehqz t ghqz t od (2) chip enable or output enable high to output hi-z 25 ns t wlqz t odw (2) output hi-z from we 25 ns t avav t wc write cycle time 70 ns t wlwh t eleh t wp (3) we , ce pulse width 50 ns t ave l t avw l t aw address setup time 0 ns t ehax t wr1 write recovery time 15 ns t whax t wr2 address hold time from we 0ns t whqx t oew output active from we 5ns t dveh t dvwh t ds (4) data setup time 30 ns t whdx t dh1 (4) data hold time from we 0ns t ehdx t dh2 (4) data hold time from ce 10 ns
13/24 m48t248y, m48t248v table 8. memory ac characteristics, m48t248v note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. these parameters are sampled with a 5 pf load are not 100% tested. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t wr is a function of the latter occurring edge of we or ce . 5. t dh and t ds are measured from the earlier of ce or we going high. symbol parameter (1) m48t248vC85 unit min max t avav t rc read cycle time 85 ns t avqv t acc access time 85 ns t elqv t co chip enable low to output valid 85 ns t glqv t oe output enable low to output valid 45 ns t elqx t glqx t coe chip enable or output enable low to output transition 5 ns t axqx t oh output hold from address change 5 ns t ehqz t ghqz t od (2) chip enable or output enable high to output hi-z 35 ns t wlqz t odw (2) output hi-z from we 30 ns t avav t wc write cycle time 85 ns t wlwh t wp1 (3) write enable pulse width 65 ns t eleh t wp2 chip enable pulse width 75 ns t ave l t avw l t aw address setup time 0 ns t ehax t wr1 (4) write recovery time 15 ns t whax t wr2 (4) address hold time from we 5ns t whqx t oew output active from we 5ns t dveh t dvwh t ds (5) data setup time 35 ns t whdx t dh1 (5) data hold time from we 0ns t ehdx t dh2 (5) data hold time from ce 15 ns
m48t248y, m48t248v 14/24 data retention mode data can be read or written only when v cc is greater than v pfd . when v cc is below v pfd (the point at which write protection occurs), the clock registers and the sram are blocked from any ac- cess. when v cc falls below the battery switch over threshold (v so ), the device is switched from v cc to battery backup (v bat ). rtc operation and sram data are maintained via battery backup un- til power is stable. all control, data, and address signals must be powered down when v cc is pow- ered down. the lithium power source is designed to provide power for rtc activity as well as rtc and ram data retention when v cc is absent or unstable. the capability of this source is sufficient to power the device continuously for the life of the equip- ment into which it has been installed. for specifi- cation purposes, life expectancy is ten (10) years at 25c with the internal oscillator running without v cc . each unit is shipped with its energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pfd , the energy source is enabled for battery backup operation. the actual life expectancy will be much longer if no battery energy is used (e.g., when v cc is present). figure 9. power down/up mode ac waveforms table 9. power down/up trip points dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. at 25c, v cc = 0v; the expected t dr is defined as cumulative time in the absence of v cc with the clock oscillator running. symbol parameter (1) min max unit t rec v pfd (max) to ce low 1.5 2.5 ms t f v pfd (max) to v pfd (min) v cc fall time 300 m s t fb v pfd (min) to v so v cc fall time 10 m s t r v pfd (min) to v pfd (max) v cc rise time 0 m s t pd ce high to power-fail 0 m s t dr (2) expected data retention time 10 years tdr tf trec tr tpd tfb v so v cc ce v pfd (max) v pfd (min) ai04236
15/24 m48t248y, m48t248v phantom clock operation communication with the phantom clock is estab- lished by pattern recognition of a serial bit-stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on dq0. all accesses which occur prior to recognition of the 64-bit pattern are directed to memory. after recognition is established, the next 64 read or write cycles either extract or update data in the clock while disabling the memory. data transfer to and from the timekeeping function is accomplished with a serial bit-stream under con- trol of chip enable (ce ), output enable (oe ), and write enable (we ). initially, a read cycle using the ce and oe control of the clock starts the pat- tern recognition sequence by moving the pointer to the first bit of the 64-bit comparison register (see figure 10, page 16). next, 64 consecutive write cycles are executed using the ce and we control of the device. these 64 write cycles are used only to gain access to the clock. therefore, any address to the memory is acceptable. however, the write cycles gener- ated to gain access to the phantom clock are also writing data to a location in the mated ram. the preferred way to manage this requirement is to set aside just one address location in ram as a phan- tom clock scratch pad. when the first write cycle is executed, it is com- pared to bit 1 of the 64-bit comparison register. if a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. if a match is not found, the pointer does not ad- vance and all subsequent write cycles are ig- nored. if a read cycle occurs at any time during pattern recognition, the present sequence is abort- ed and the comparison register pointer is reset. pattern recognition continues for a total of 64 write cycles as described above until all of the bits in the comparison register have been matched. with a correct match for 64-bits, the phantom clock is enabled and data transfer to or from the timekeeping registers can proceed. the next 64 cycles will cause the phantom clock to ei- ther receive or transmit data on dq0, depending on the level of the oe pin or the we pin. cycles to other locations outside the memory block can be interleaved with ce cycles without interrupting the pattern recognition sequence or data transfer se- quence to the phantom clock.
m48t248y, m48t248v 16/24 figure 10. comparison register definition note: the odds of this pattern being accidentally duplicated and sending aberrant entries to the rtc is less than 1 in 10 19 . this pattern is sent to the clock lsb to msb. 7 65 432 1 0 byte 0 byte 1 by te 2 byte 3 by te 4 by te 5 byte 6 by te 7 hex value 0 1 0 0 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 c5 3a a3 5c c5 3a a3 5c ai04262
17/24 m48t248y, m48t248v clock register information clock information is contained in eight registers of 8 bits, each of which is sequentially accessed one (1) bit at a time after the 64-bit pattern recognition sequence has been completed. when updating the clock registers, each must be handled in groups of 8 bits. writing and reading individual bits within a register could produce erroneous results. these read/write registers are defined in the clock register map (see table 10). data contained in the clock registers is in binary coded decimal format (bcd). reading and writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of register 0 and ending with bit 7 of register 7. clock accuracy the rtc is guaranteed to keep time accuracy to with 1 minute per month at 25c. the clock is fac- tory-tuned with special calibration elements, and does not require additional calibration. moderate temperature deviation will have a negligible effect in most applications. am-pm/12/24 mode bit 7 of the hours register is defined as the 12-hour or 24-hour mode select bit. when it is high, the 12- hour mode is selected. in the 12-hour mode, bit 5 is the am/pm bit with the logic high being pm. in the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours). oscillator and reset bits bits 4 and 5 of the day register are used to control the reset and oscillator functions. bit 4 controls the reset pin input. when the reset bit is set to logic '1,' the reset input pin is ignored. when the reset bit logic is set to '0,' a low input on the reset pin will cause the device to abort data transfer without changing data in the timekeeping registers. reset operates independently of all other inputs. bit 5 controls the oscillator. when set to logic '0,' the os- cillator turns on and the rtc/calendar begins to increment. zero bits registers 1, 2, 3, 4, 5, and 6 contain one (1) or more bits that will always read logic '0.' when writ- ing to these locations, either a logic '1' or '0' is ac- ceptable. table 10. phantom clock register map keys: a/p = am/pm bit 12/24 = 12 or 24-hour mode bit osc = oscillator bit rst = reset bit 0 = must be set to '0' function/range bcd format register d7 d6 d5 d4 d3 d2 d1 d0 0 0.1 seconds 0.01 seconds seconds 00-99 1 0 10 seconds seconds seconds 00-59 2 0 10 minutes minutes minutes 00-59 3 12/24 0 10 / a/p hrs hours (24 hour format) hours 01-12/ 00-23 400osc rst 0 day of the week day 01-7 5 0 0 10 date date: day of the month date 01-31 6 0 0 0 10m month month 01-12 7 10 years year year 00-99
m48t248y, m48t248v 18/24 figure 11. phantom clock read cycle figure 12. phantom clock write cycle figure 13. phantom clock reset data output valid we ce oe q tcw tco trc tow tcoe todo trr tod toe toee ai04259 data input stable oe d ce twp twc tcw tdh twr twr we t dh tds ai04261 trst rst ai04235
19/24 m48t248y, m48t248v table 11. phantom clock ac characteristics (m48t248y) note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. these parameters are sampled with a 5 pf load and are not 100% tested. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t wr is a function of the latter occurring edge of we or ce . 5. t dh and t ds are measured from the earlier of ce or we going high. symbol parameter (1) min typ max unit t avav t rc read cycle time 65 ns t elqv t co ce access time 55 ns t glqv t oe oe access time 55 ns t elqx t coe ce to output low z 5 ns t glqx t oee oe to output low z 5 ns t ehqz t od (2) ce to output high z 25 ns t ghqz t odo (2) oe to output high z 25 ns t rr read recovery 10 ns t avav t wc write cycle time 65 ns t wlwh t wp (3) write pulse width 55 ns t ehax t wr (4) write recovery 10 ns t dveh t ds (5) data setup time 30 ns t whdx t dh1 (5) data hold time from we 0ns t ehdx t dh2 (5) data hold time from ce 0ns t eleh t cw ce pulse width 55 ns t rst rst pulse width 65 ns
m48t248y, m48t248v 20/24 table 12. phantom clock ac characteristics (m48t248v) note: 1. valid for ambient operating temperature: t a = 0 to 70c; v cc = 4.5 to 5.5v or 3.0 to 3.6v (except where noted). 2. these parameters are sampled with a 5 pf load and are not 100% tested. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t wr is a function of the latter occurring edge of we or ce . 5. t dh and t ds are measured from the earlier of ce or we going high. symbol parameter (1) min typ max unit t avav t rc read cycle time 85 ns t elqv t co ce access time 85 ns t glqv t oe oe access time 85 ns t elqx t coe ce to output low z 5 ns t glqx t oee oe to output low z 5 ns t ehqz t od (2) ce to output high z 30 ns t ghqz t odo (2) oe to output high z 30 ns t rr read recovery 20 ns t avav t wc write cycle time 85 ns t wlwh t wp (3) write pulse width 60 ns t ehax t wr (4) write recovery 20 ns t dveh t ds (5) data setup time 35 ns t whdx t dh1 (5) data hold time from we 0ns t ehdx t dh2 (5) data hold time from ce 0ns t eleh t cw ce pulse width 65 ns t rst rst pulse width 85 ns
21/24 m48t248y, m48t248v package mechanical information figure 14. pmdip32 C 32-pin plastic module dip, package outline note: drawing is not to scale. table 13. pmdip32 C 32-pin plastic module dip, package mechanical data symb mm inches typ min max typ min max a 9.27 9.52 0.365 0.375 a1 0.38 C 0.015 C b 0.43 0.59 0.017 0.023 c 0.20 0.33 0.008 0.013 d 42.42 43.18 1.670 1.700 e 18.03 18.80 0.710 0.740 e1 2.29 2.79 0.090 0.110 e3 34.29 41.91 1.350 1.650 ea 14.99 16.00 0.590 0.630 l 3.05 3.81 0.120 0.150 s 1.91 2.79 0.075 0.110 n3232 pmdip a1 a l be1 d e n 1 ea e3 s c
m48t248y, m48t248v 22/24 part numbering table 14. ordering information example for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m48t 248y C70 pm 1 tr device type m48t supply voltage and write protect voltage 248y = v cc = 4.5 to 5.5v; v pfd = 4.25 to 4.50v 248v = v cc = 3.0 to 3.6v; v pfd = 2.80 to 2.97v speed C70 = 70ns (m48t248y) C85 = 85ns (m48t248v) package pm = pmdip32 temperature range 1 = 0 to 70c shipping method for soic blank = tubes tr = tape & reel
23/24 m48t248y, m48t248v revision history table 15. document revision history date rev. # revision details june 2001 1.0 first issue 28-mar-03 2.0 v2.2 template applied; test condition updated (table 9)
m48t248y, m48t248v 24/24 m48t248, m48t248y, m48t248v, 48t248, 48t248y, 48t248v, t248, t248y, t248v, timekeeper, timekeeper, timekeep- er, timekeeper, timekeeper, timekeeper, timekeep- er, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, timekeeper, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, nvram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, sram, 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switchover, switchover, switchover, switchover, switchover, backup, backup, backup, backup, backup, backup, backup, backup, backup, back- up, backup, backup, backup, backup, backup, backup, backup, backup, backup, backup,5v,5v,5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 5v, 3.3v, 3.3v, 3.3v, 3.3v, 3.3v, 3.3v, 3.3v, 3.3v, 3.3v, 3.3v information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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